Design of a silicon cochlea system with biologically faithful response

This paper presents the design and simulation results of a silicon cochlea system that has closely similar behavior as the real cochlea. A cochlea filter-bank based on the improved three-stage filter cascade structure is used to model the frequency decomposition function of the basilar membrane; a filter tuning block is designed to model the adaptive response of the cochlea; besides, an asynchronous event-triggered spike codec is employed as the system interface with bank-end spiking neural networks. As shown in the simulation results, the system has biologically faithful frequency response, impulse response, and active adaptation behavior; also the system outputs multiple band-pass channels of spikes from which the original sound input can be recovered. The proposed silicon cochlea is feasible for analog VLSI implementation so that it not only emulates the way that sounds are preprocessed in human ears but also is able match the compact physical size of a real cochlea

Biomimetic cochlea filters : from modelling, design to analogue VLSI implementation

This thesis presents a novel biomimetic cochlea filter which closely resembles the biological cochlea behaviour. The filter is highly feasible for analogue very-large-scale integration (VLSI) circuits, which leads to a micro-watt-power and millimetre-sized hardware implementation. By virtue of such features, the presented filter contributes to a solid foundation for future biologically-inspired audio signal processors. Unlike existing works, the presented filter is developed by taking direct inspirations from the physiologically measured results of the biological cochlea. Since the biological cochlea has prominently different characteristics of frequency response from low to high frequencies, the biomimetic cochlea filter is built by cascading three sub-filters accordingly: a 2nd-order bandpass filter for the constant gentle low-frequency response, a 2nd-order tunable low-pass filter for the variable and selective centre frequency response and a 5th-order elliptic filter for the ultra-steep roll-off at stop-band. As a proof of concept, a biomimetic cochlea filter bank is built to process audio signals, which demonstrates the highly discriminative spectral decomposition and high-resolution time-frequency analysis capabilities similar to the biological cochlea. The filter has simple representation in the Laplace domain which leads to a convenient analogue circuit realisation. A floating-active-inductor circuit cell is developed to build the corresponding RLC ladder for each of the three sub-filters. The circuits are designed based on complementary metal-oxide-semiconductor (CMOS) transistors for VLSI implementation. Non-ideal factors of CMOS transistors including parasitics, noise and mismatches are extensively analysed and consciously considered in the circuit design. An analogue VLSI chip is successfully fabricated using 0.35μ m CMOS process. The chip measurements demonstrate that the centre frequency response of the filter has about 20 dB wide gain tuning range and a high quality factor reaching maximally over 19. The filter has a 20 dB/decade constant gentle low-frequency tail and an over 300 dB/decade sharp stop-band roll-off slope. The measured results agree with the filter model expectations and are comparable with the biological cochlea characteristics. Each filter channel consumes as low as 59.5 ~90μ Wpower and occupies only 0.9 mm2 area. Besides, the biomimetic cochlea filter chip is characterised from a wide range of angles and the experimental results cover not only the auditory filter specifications but also the integrated circuit design considerations. Furthermore, following the progressive development of the acoustic resonator based on microelectro- mechanical systems (MEMS) technology, a MEMS-CMOS implementation of the proposed filter becomes possible in the future. A key challenge for such implementation is the low sensing capacitance of the MEMS resonator which suffers significantly from sensitivity degradation due to the parasitic capacitance. A novel MEMS capacitive interface circuit chip is additionally developed to solve this issue. As shown in the chip results, the interface circuit is able to cancel the parasitic capacitance and increase the sensitivity of capacitive sensors by 35 dB without consuming any extra power. Besides, the chopper-stabilisation technique is employed which effectively reduces the circuit flicker noise and offsets. Due to these features, the interface circuit chip is capable of converting a 7.5 fF capacitance change of a 1-Volt-biased 0.5 pF capacitive sensor pair into a 0.745 V signal-conditioned output while consuming only 165.2μ W power

A floating active inductor based CMOS cochlea filter with high tunability and sharp cut-off

This paper presents the design of a CMOS cochlea filter channel which achieves high tunability, sharp stopband cutoff and low power consumption with the use of floating active inductor (FAI) as the basic building block. Simulation results show that over 40dB of gain enhancement together with 20% frequency tuning can be achieved at the same time by adjusting only one circuit parameter. A fifth-order elliptic filter providing a stop-band slope of 65.4 ∼ 139.8 dB/octave is used as the last stage of the cochlea filter. The power consumption of the cochlea filter channel is 86μW.</p

Spike-based analog-digital neuromorphic information processing system for sensor applications

A spiking-neuron-based system that combines analog and digital multi-processor implementations for the bio-inspired processing of sensors is reported. This combination allows creating a powerful bio-inspired multiple-input sensor processing system for environment perception applications. The analog front-end encodes the input signal in a signed spike representation, which is further processed by means of a digital Spiking Neural Network (SNN) on a Single-Instruction Multiple-Data (SIMD) multiprocessor. The spike distribution for both systems is based on Address-Event Representation (AER) scheme, asynchronous for the Analog Pre-Processor (APP) and synchronous for the Digital Multi-Processor (DMP), synchronized by means of an AER transceiver. A proof-of-concept application of the system being able to process sensory information has been demonstrated. The system utilizes 30-neurons emulated by the DMP to process spike-encoded information provided by its analog counterpart, enabling the feature extraction of the input signal. The frequency detection capability of the system is experimentally reported

Reduced-complexity equalization for EDGE

SIGLEAvailable from British Library Document Supply Centre- DSC:DXN064194 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Analog VLSI circuit implementation of an adaptive neuromorphic olfaction chip

In this paper, we present the analog circuit design and implementation of the components of an adaptive neuromorphic olfaction chip. A chemical sensor array employing carbon black composite sensing materials with integrated signal processing circuitry forms the front end of the chip. The sensor signal processing circuitry includes a dc offset cancellation circuit to ameliorate loss of measurement range associated with chemical sensors. Drawing inspiration from biological olfactory systems, the analog circuits used to process signals from the on-chip odor sensors make use of temporal "spiking" signals to act as carriers of odor information. An on-chip spike time dependent learning circuit is integrated to dynamically adapt weights for odor detection and classification. All the component subsystems implemented on chip have been successfully tested in silicon

A Power-Efficient Capacitive Read-Out Circuit with Parasitic-Cancellation for MEMS Cochlea Sensors

This paper proposes a solution for signal read-out in the MEMS cochlea sensors that have very small sensing capacitance and do not have differential sensing structures. The key challenge in such sensors is the significant signal degradation caused by the parasitic capacitance at the MEMS-CMOS interface. Therefore, a novel capacitive read-out circuit with parasitic-cancellation mechanism is developed; the equivalent input capacitance of the circuit is negative and can be adjusted to cancel the parasitic capacitance. Chip results prove that the use of parasitic-cancellation is able to increase the sensor sensitivity by 35 dB without consuming any extra power. In general, the circuit follows a low-degradation low-amplification approach which is more power-efficient than the traditional high-degradation high-amplification approach; it employs parasitic-cancellation to reduce the signal degradation and therefore a lower gain is required in the amplification stage. Besides, the chopper-stabilization technique is employed to effectively reduce the low-frequency circuit noise and DC offsets. As a result of these design considerations, the prototype chip demonstrates the capability of converting a 7.5 fF capacitance change of a 1-Volt-biased 0.5 pF capacitive sensor pair into a 0.745 V signal-conditioned output at the cost of only 165.2 &mu;W power consumption. &copy; 2015 IEEE

A low-noise interface circuit for MEMS cochlea-mimicking acoustic sensors

This paper proposes a low-noise MEMS interface circuit which has very small parasitic capacitance at the input node. The circuit presented is suitable for the MEMS cochlea-mimicking acoustic sensors which are highly parasitic-sensitive due to their low intrinsic sensing capacitance. In order to reduce the electronic noise of the interface circuit, chopper stabilization technique is implemented, and an effective method to optimize the critical transistor size for best noise performance is derived. Simulation results show that, for a MEMS sensing structure with 200 fF static capacitance, the interface circuit achieves a 0.72 aF equivalent capacitance noise floor over 100 Hz to 20 kHz audio bandwidth.</p

Design of a Spike Event Coded RGT Microphone for Neuromorphic Auditory Systems

This paper presents the design of a spike event coded resonant gate transistor microphone system for neuromorphic auditory applications. The microphone system employs an array of resonant gate transistors (RGT) to transduce acoustic input directly into bandpass filtered analog outputs. The bandpass filtered analog outputs are encoded as spike time events by a spike event coder and are then transmitted asynchronously by using the Address Event Representation (AER) protocol. The microphone system is designed to receive external inputs in the spike time domain to actively control the RGT response, a feature not present in other MEMS microphone systems implemented so far. System level simulations showing the response of the RGT sensor model and its spike event coded response are presented

Spike-based analog-digital neuromorphic information processing system for sensor applications

A spiking-neuron-based system that combines analog and digital multi-processor implementations for the bio-inspired processing of sensors is reported. This combination allows creating a powerful bio-inspired multiple-input sensor processing system for environment perception applications. The analog front-end encodes the input signal in a signed spike representation, which is further processed by means of a digital Spiking Neural Network (SNN) on a Single-Instruction Multiple-Data (SIMD) multiprocessor. The spike distribution for both systems is based on Address-Event Representation (AER) scheme, asynchronous for the Analog Pre-Processor (APP) and synchronous for the Digital Multi-Processor (DMP), synchronized by means of an AER transceiver. A proof-of-concept application of the system being able to process sensory information has been demonstrated. The system utilizes 30-neurons emulated by the DMP to process spike-encoded information provided by its analog counterpart, enabling the feature extraction of the input signal. The frequency detection capability of the system is experimentally reported.Peer Reviewe